JPH0220022B2 - - Google Patents

Info

Publication number
JPH0220022B2
JPH0220022B2 JP56500047A JP50004781A JPH0220022B2 JP H0220022 B2 JPH0220022 B2 JP H0220022B2 JP 56500047 A JP56500047 A JP 56500047A JP 50004781 A JP50004781 A JP 50004781A JP H0220022 B2 JPH0220022 B2 JP H0220022B2
Authority
JP
Japan
Prior art keywords
waveform
gate
output
flop
incoming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56500047A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56501429A (en]
Inventor
Tomasu Aaru Utsudowaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of JPS56501429A publication Critical patent/JPS56501429A/ja
Publication of JPH0220022B2 publication Critical patent/JPH0220022B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
JP56500047A 1979-10-29 1980-10-20 Expired - Lifetime JPH0220022B2 (en])

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/088,947 US4320525A (en) 1979-10-29 1979-10-29 Self synchronizing clock derivation circuit for double frequency encoded digital data

Publications (2)

Publication Number Publication Date
JPS56501429A JPS56501429A (en]) 1981-10-01
JPH0220022B2 true JPH0220022B2 (en]) 1990-05-07

Family

ID=22214444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56500047A Expired - Lifetime JPH0220022B2 (en]) 1979-10-29 1980-10-20

Country Status (5)

Country Link
US (1) US4320525A (en])
EP (1) EP0045749B1 (en])
JP (1) JPH0220022B2 (en])
DE (1) DE3070926D1 (en])
WO (1) WO1981001226A1 (en])

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE32432E (en) * 1979-12-28 1987-06-02 Sony Corporation Method and apparatus for decoding digital data
US4428007A (en) 1979-12-28 1984-01-24 Sony Corporation Method and apparatus for decoding digital data
US4355398A (en) * 1980-12-17 1982-10-19 Ncr Corporation Real time clock recovery circuit
US4468752A (en) * 1981-09-21 1984-08-28 Tandy Corporation Data synchronization apparatus
US4443883A (en) * 1981-09-21 1984-04-17 Tandy Corporation Data synchronization apparatus
US4449119A (en) * 1981-12-14 1984-05-15 International Business Machines Corporation Self-clocking serial decoder
DE3462741D1 (en) * 1983-03-11 1987-04-23 Cit Alcatel Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase l code, and the modified biphase code
US4547764A (en) * 1983-10-31 1985-10-15 Burroughs Corporation Pulse width decoder for double frequency encoded serial data
US4542420A (en) * 1984-01-24 1985-09-17 Honeywell Inc. Manchester decoder
FR2567697B1 (fr) * 1984-07-13 1991-03-29 Servel Michel Dispositif de localisation des transitions d'un signal de donnees par rapport a un signal d'horloge et mecanisme de cadrage comprenant un tel dispositif
FR2567696B1 (fr) * 1984-07-13 1991-06-28 Thomas Alain Dispositif de cadrage automatique d'horloge locale par rapport a un signal de donnees et circuit d'echantillonnage en comportant application
US4748348A (en) * 1986-12-29 1988-05-31 Tektronix, Inc. Multi-level pattern detector for a single signal
EP0299024A4 (en) * 1987-01-05 1990-11-28 Grumman Aerospace Corporation High speed data-clock synchronization processor
US4841551A (en) * 1987-01-05 1989-06-20 Grumman Aerospace Corporation High speed data-clock synchronization processor
US4864588A (en) * 1987-02-11 1989-09-05 Hillier Technologies Limited Partnership Remote control system, components and methods
US4788605A (en) * 1987-03-30 1988-11-29 Honeywell Inc. Receive Manchester clock circuit
US4763338A (en) * 1987-08-20 1988-08-09 Unisys Corporation Synchronous signal decoder
DE3728655A1 (de) * 1987-08-27 1989-03-09 Thomson Brandt Gmbh Verfahren und/oder einrichtung zum demodulieren eines biphasesignales
US4843331A (en) * 1987-08-28 1989-06-27 Hughes Aircraft Company Coherent digital signal blanking, biphase modulation and frequency doubling circuit and methodology
US4809301A (en) * 1987-11-25 1989-02-28 The United States Of America As Represented By The Secretary Of The Air Force Detection apparatus for bi-phase signals
US4868569A (en) * 1987-12-15 1989-09-19 Schlumberger Well Services Biphase digital look-ahead demodulating method and apparatus
US5065041A (en) * 1989-01-05 1991-11-12 Bull Hn Information Systems Inc. Timing generator module
US5146478A (en) * 1989-05-29 1992-09-08 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
JP2653177B2 (ja) * 1989-06-22 1997-09-10 日産自動車株式会社 雑音除去回路
US4992790A (en) * 1989-09-19 1991-02-12 Schlumberger Technology Corporation Digital phase-locked loop biphase demodulating method and apparatus
US5185766A (en) * 1990-04-24 1993-02-09 Samsung Electronics Co., Ltd. Apparatus and method for decoding biphase-coded data
US5524109A (en) * 1991-06-20 1996-06-04 Bay Networks, Incorporated Token ring concentrator having retiming function
JPH09116338A (ja) * 1995-10-19 1997-05-02 Toshiba Corp 遅延型ｆｍ復調回路
DE10121855A1 (de) * 2001-05-04 2003-02-13 Atmel Germany Gmbh Verfahren zur Übertragung von Daten
TWI257482B (en) * 2004-12-15 2006-07-01 Spirox Corp Method and apparatus for measuring jitter of signal

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271750A (en) * 1962-12-13 1966-09-06 Ibm Binary data detecting system
US3271742A (en) * 1963-11-06 1966-09-06 Ibm Demodulation system
US3405391A (en) * 1964-12-21 1968-10-08 Ibm Double frequency detection system
US3480869A (en) * 1966-12-27 1969-11-25 Bell Telephone Labor Inc Timing recovery circuit for use in frequency-modulated,differentially coherent phase modulation (fm-dpm) communication system
US3611158A (en) * 1969-11-12 1971-10-05 Collins Radio Co Signal pulse trigger-gating edge jitter rejection circuit
US3947878A (en) * 1972-03-17 1976-03-30 General Instrument Corporation Self-clocking NRZ recording and reproduction system
US4010323A (en) * 1975-10-29 1977-03-01 Bell Telephone Laboratories, Incorporated Digital timing recovery
US4019149A (en) * 1976-01-16 1977-04-19 Bell Telephone Laboratories, Incorporated Correlative data demodulator
US4185273A (en) * 1977-07-27 1980-01-22 The United States Of America As Represented By The Secretary Of The Navy Data rate adaptive control device for Manchester code decoders
US4234897A (en) * 1978-10-05 1980-11-18 Ampex Corporation DC Free encoding for data transmission
US4313206A (en) * 1979-10-19 1982-01-26 Burroughs Corporation Clock derivation circuit for double frequency encoded serial digital data

Also Published As

Publication number Publication date
EP0045749A1 (en) 1982-02-17
WO1981001226A1 (en) 1981-04-30
US4320525A (en) 1982-03-16
EP0045749A4 (en) 1982-04-29
DE3070926D1 (en) 1985-09-05
EP0045749B1 (en) 1985-07-31
JPS56501429A (en]) 1981-10-01

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